One of the key performance parameters for precision voltage references and comparators is the temperature coefficient (TC). The TC parameter specifies the amount of voltage change which occurs as a result of a change in temperature. TC for a given component may be positive, negative, or may change direction over various temperature ranges.
The bandgap and buried zener are two known methods for implementing voltage references. The bandgap and buried zener voltage references utilize special bipolar or BiCMOS process technologies. These types of references require various trimming methods, e.g., laser trimmed thin-film resistors or metal fuses, for achieving close to 1 mV initial accuracy and a TC at or below 5 ppm per degree C.
More recently, a precision floating gate voltage reference (FGREF) has been implemented on EEPROM CMOS technology. A precision floating gate voltage reference stores a known voltage on a floating capacitor tied to the input of an opamp. Tunnel diodes are typically used as switches to charge the floating capacitor during the programming (set) mode. The TC of the FGREF depends on the TC of the storage capacitor. In order to achieve close to zero TC, known circuits and methods utilize a mix of different types of capacitors for causing the composite TC of the capacitors to be near zero.
FIG. 1 illustrates a simplified schematic of an ideal prior art floating gate voltage reference circuit 10. The charge on a capacitor C is set at the factory by using one or more tunnel diodes, as at S0, as an ideal switch for coupling an input voltage Vs0 to capacitor C in a programming (set) mode. Capacitor C holds the programmed voltage, Vs, at a storage node, node 11, which is coupled to the input of a unity gain buffer 12. The unity gain buffer 12 is provided to isolate the floating gate storage node 11 from a load at the output terminal 14 of buffer 12. At the conclusion of the set mode, the output Vout of the voltage reference circuit 10 at node 14 has been set to a voltage that is a function of, and preferably is equal to the input set voltage Vso received at an input terminal 16.
The temperature coefficient of voltage reference circuit 10 is a function of the TC of the capacitor C. The TC of capacitor C is typically fairly low (˜+20 ppm/C) for Poly1/Poly2 capacitors in CMOS technology. Since the storage node 11 is floating and fully protected from any outside or inside contact, charge conservation principles can be applied to calculate the TC of Vout due to the change in the value of Capacitor C with temperature. A set of Equations 1 below shows that TC of Vout is the negative of the TC of the capacitor C.
EQUATIONS 1: Charge at Storage Node 11 is given by Q(t0)=constant, determined at programming time and a selected temperature, t0.                Assume: C(t)=C0(1+α(t−t0)), where t0=25° C. (ambient temperature), where t is the die temperature, C0 is the capacitance of capacitor C, and α is the TC of capacitor C.        
            Q      ⁡              (        t        )              =                                        C            0                    ·                                    V              S                        ⁡                          (              25              )                                      ⁢                                  ∴                  Q          ⁡                      (            t            )                              =                                    C            ⁡                          (              t              )                                ·                                    V              S                        ⁡                          (              t              )                                      =                              C            0                    ·                                    V              S                        ⁡                          (              25              )                                                                                    ⇒                                          V                S                            ⁡                              (                t                )                                              =                                                    C                0                            ·                                                V                  S                                ⁡                                  (                  25                  )                                                                    C              ⁡                              (                t                )                                                                                  =                                                    C                0                            ·                                                V                  S                                ⁡                                  (                  25                  )                                                                                    C                0                            ⁡                              (                                  1                  +                                                            α                      ·                      Δ                                        ⁢                                                                                  ⁢                    t                                                  )                                                                    or      ⁢                          ⁢                        V          S                ⁡                  (          t          )                      ≅                            V          S                ⁡                  (          25          )                    ·              (                  1          -                                    α              ·              Δ                        ⁢                                                  ⁢            t                          )                        or      ⁢                          ⁢                        V          R                ⁡                  (          t          )                      =                            V          R                ⁡                  (          25          )                    ·              (                  1          -                                    α              ·              Δ                        ⁢                                                  ⁢            t                          )                        TC              V        R              =                            1                      V            R                          ·                              ∂                          V              R                                            ∂            t                              =              -        α                  cos    ⁢          φ      ^        ⁢    cos    ⁢                  ⁢          φ      ^      
Since the TC of Vout is the negative of the TC of the capacitor C, in order to get zero TC at Vout, capacitors with near-zero TC are required. In one known method, two different types of capacitors are combined for minimizing TC. FIG. 2a illustrates an exemplary prior art circuit 20 utilizing a differential scheme for achieving a minimum TC. The differential scheme with feedback is utilized in order to address drawbacks of the circuit 10, including common mode noise of the buffer amplifier 12 over a wide range of reference voltage values. The combined composite capacitor comprises a Poly1 to Poly2 capacitor, referred to as CP type capacitor, connected in parallel with a Poly1 to N+ Diffusion capacitor, referred to as CPD type capacitor, as illustrated symbolically in FIG. 2b. The CP capacitor typically has a TC of +20 ppm/deg C. and the CPD capacitor typically has a TC of −10 ppm/deg C. TC. This known method includes adjusting the area ratios of CP to CPD in order to cause the TC at Vout to approach zero, in accordance with a set of Equations 2.
EQUATIONS 2: Where t=die Temperature, t0=ambient temperature during the programming of the voltage reference circuit, Δt=t−t0, α=TC of a CP type capacitor, and β=TC of a CPD type capacitor:
      C    =          CP      +      CPD            CP    =                  CP        0            ⁡              (                  1          +                                    α              ·              Δ                        ⁢                                                  ⁢            t                          )                  CPD    =                  CPD        0            ⁡              (                  1          -                                    β              ·              Δ                        ⁢                                                  ⁢            t                          )                                                      ∴            C                    =                                    (                                                CP                  0                                +                                  CPD                  0                                            )                        +                                          (                                                      α                    ·                                          CP                      0                                                        -                                      β                    ·                                          CPD                      0                                                                      )                            ⁢              Δ              ⁢                                                          ⁢              t                                                                    =                                    (                                                CP                  0                                +                                  CPD                  0                                            )                        ⁢                          (                              1                +                                                                                                                              α                          ·                                                      CP                            0                                                                          -                                                  β                          ·                                                      CPD                            0                                                                                                                                                CP                          0                                                +                                                  CPD                          0                                                                                      ·                    Δ                                    ⁢                                                                          ⁢                  t                                            )                                                      TC      eq        =          γ      =                                    α            ·                          CP              0                                -                      β            ·                          CPD              0                                                            CP            0                    +                      CPD            0                                              Thus, by choosing CP0/CPD0 appropriately, one can get a Zero TC value.        
In FIG. 2a, the switches S0 and S1 are coupled between an input terminal 24 and respective inputs of an opamp 22 for setting a set voltage, Vs0 on a storage node 21 and on the inverting input of opamp 22, respectively. Storage capacitors CPD0 and CP0 are connected in parallel between node 21 and ground. Feedback capacitors CPD1 and CP1 are connected in parallel between the negative input of opamp 22 and, via a switch S2, the output of circuit 20. The switch S2 is used to set the output end of the feedback capacitor CP1 to a desired reference voltage value, VR.
As shown in FIG. 2a, when two different types of capacitors are used to achieve close to a zero TC, it is known to use a mix of CP and CPD capacitors. As is also seen, this method is applied to both the storage capacitor in the circuit as well as the feedback capacitor. The TC of the CPD capacitor has been found, however, to be dependent on the applied voltage. Consequently, attempting to use two types of capacitors, e.g., as shown in FIG. 2a, to obtain zero TC for different output voltage values, is very challenging and is mostly an empirical exercise.
What is therefore needed is a method for TC cancellation for a floating gate voltage reference that uses only one type of capacitor so as to provide a predictable and programmable TC for the overall voltage reference generator circuit. What is also needed is an analog floating gate voltage reference circuit for accurately programming a desired charge level on a floating gate and for making TC reduction methods more reliable and repeatable for different output voltage values.